利用状态机的VHDL描述方法设计一个序列检测器,要求连续输入3个或3个以上的1时输出为1，否则为0。谁会啊！

Answer 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xulie is
port(clk,reset:in std_logic;
input:in std_logic;
result:out std_logic);
end entity;
architecture art of xulie is
type states is (s0,s1,s2);
signal state:states;
begin
process(clk,reset,state,input)
varialbe cnt:integer;
begin
if reset='1' than
state<=s0;
elsif clk'event and clk='1' then
case state is
when s0=> output<='0';cnt:=0;state<=s1;
when s1=>if input='1' then
cnt:=cnt+1;
state<=s1;
else state<=s2;
end if;
when s2=>if cnt>=3 then
output<='1';
else output<='0';
end if;
state<=s0;
when others=>state<=s0;
end case;
end if;
end process;
end art;