Verilog编一个八位移位寄存器，单向的就可以了

Question

如题，八位的输入

Answer 1

module reg_8(clk,reset,data_in,data_out);

input clk,reset;
input data_in;
output [7:0]data_out;

always@(posedge clk)
begin
if(reset)
data_out<=0;
else
data_out<={data_out[7:1],data_in};
end
endmodule