求4位多功能移位寄存器VHDL程序

Question

功能为SaSb=00时，右移；SaSb=01时左移；SaSb=10时，同步清零；SaSb=11时，同步置数。急求！！！

Answer 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity yw is
port(
data:in std_logic_vector(3 downto 0);--待置数
clk:in std_logic;
Sa :in std_logic;
Sb :in std_logic;
shift_Bit: in std_logic; --要移入的数据
qout :buffer std_logic_vector(3 downto 0));
end yw;

architecture behave of yw is
signed mode : std_logic_vector(1 downto 0);
begin

mode <= Sa & Sb;

process(clk)
begin
if(clk'event and clk='1')then
case mode is
when"10"=>qout<="0000"; --清零
when"11"=>qout<=data; --置数
when"00"=>qout<=shift_Bit & qout(3 downto 1); --右移
when"01"=>qout<=qout(2 downto 0) &shift_Bit ;--左移
when others=>null;
end case;
else
qout<=qout
end if;
end process;

end behave；