用Verilog编写8位的1024存储单元的双口ROM 出错

Question

要使标号为1的控制线 cs1，wr1,rd1,数据线data1，地址线add1优先级高于标号为2的。

以下是我写的，我感觉不太对，就是读写的优先操作有些问题，不过没有语法错误
module ram_1024(cs1,cs2,wr1,rd1,wr2,rd2,data1,data2,add1,add2);

input cs1,cs2,wr1,rd1,wr2,rd2;
inout[7:0]data1,data2;
input[9:0]add2;
input[9:0]add1;
reg[7:0] ram[1023:0];

assign data1=((!cs1&&!rd1)&&(cs1||wr1)&&(cs2||wr2))?ram[add1]:8'bzz;
assign data2=((!cs2&&!rd2)&&(cs1||wr1)&&(cs2||wr2))?ram[add2]:8'bzz;

always@( cs1 or wr1 or wr2 or cs2 )
begin
if(add1==add2)
begin
if(!cs1&&!wr1) ram[add1]=data1;
else if(!cs2&&!wr2) ram[add2]=data2;
end
else if(!cs1&&!wr1) ram[add1]=data1;
else if(!cs2&&!wr2) ram[add2]=data2;
end
endmodule

还有我在quartusii中用的device是EPIC6Q240C8，当我在bdf文件中用我编的这个rom的时候会有错
Error: Design contains 14830 blocks of type logic cell. However, device contains only 5980.
以上个人理解为该器件的门少了，不能构成这么大存储空间的rom，不知对不对。
Error: Can't fit design in device

小弟我刚学，请高手指点一下
希望能给个双口rom的代码，我不胜感激。
以下的有clock，但依然通不过啊，

module RAM_TWO_IO
#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=10)
(
input [(DATA_WIDTH-1):0] data_a, data_b,
input [(ADDR_WIDTH-1):0] addr_a, addr_b,
input rd_a, wr_a,rd_b,wr_b,clk_a,clk_b,
output reg [(DATA_WIDTH-1):0] q_a, q_b
);

// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];

always @ (posedge clk_a)
begin
// Port A
if (!wr_a)
begin
ram[addr_a] <= data_a;
end
else if(!rd_a)
begin
q_a <= ram[addr_a];
end
end

always @ (posedge clk_b)
begin
// Port B

if (!wr_b)
begin
ram[addr_b] <= data_b;
end
else if(!rd_b)
begin
q_b <= ram[addr_b];
end

end
endmodule

Answer 1

quartusii查下有没这样的RAM，如果有那就直接例化。
另外你的RAM没有时钟？所以你这样写压根也不是寄存器搭建的RAM

最后想说的是，从后端考虑，用寄存器搭建的RAM timing没有例化的好

针对你的问题：直接quartus有memory的选项的,选dual port

Answer 2

双口RAM可以使用芯片内部RAM，使用寄存器阵列仅限于小容量和高速度才使用，你做的RAM已经大大的超出了EP1C6Q240的容量！！！

Answer 3

用quartus一编译、综合就可以看出你的问题所在。
你第一个程序：一堆warning不知道你有没有注意
1.always里条件没写全；
2.你有if没else，这样会综合很多latch，导致你的存储单元不够用。
这样的程序实在太糟糕了。
第二个程序：哎~ 自己看，别觉得warning不重要!!!!! 给你个提示吧：你很喜欢有if没else 也不喜欢加个复位信号

Answer 4

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Answer 5

所谓双口RAM，是在一个SRAM 存储器上具有两套完全独立的数据线、地址线和读写控制线，并允许两个独立的系统同时对该存储器进行随机性的访问。即共享式多端口存储器。
因为数据共享，就必须存在访问仲裁控制，对同一地址单元访问的时序进行控制，对存储单元数据块的访问进行权限分配等。
在你的第二个程序中，没有优先级控制，在两个always块中同时对ram变量进行赋值，这是典型的多重驱动问题。
因此，写操作必须在一个always中完成，读操作可在两个always中完成。如果不考虑先写后读，程序如下：
module ram_io2(data_a, data_b,addr_a, addr_b,rd_a, wr_a,rd_b,wr_b,clk_a,clk_b,q_a, q_b);
parameter DATA_WIDTH=8;
parameter ADDR_WIDTH=10;
input [(DATA_WIDTH-1):0] data_a, data_b;
input [(ADDR_WIDTH-1):0] addr_a, addr_b;
input rd_a, wr_a,rd_b,wr_b,clk_a,clk_b;
output [(DATA_WIDTH-1):0] q_a, q_b;
reg [(DATA_WIDTH-1):0] q_a, q_b;
// Declare the RAM variable
reg [DATA_WIDTH-1:0] mem1 [(2**ADDR_WIDTH)-1:0];
always @ (clk_a,clk_b)
begin
// WRITE
if (!wr_a)
mem1[addr_a]<=data_a;
else if(!wr_b)
mem1[addr_b]<=data_b;
end

always @ (posedge clk_a)
begin
// Port A READ
if (!rd_a)
q_a <= mem1[addr_a];
else
q_a <=8'bzz;
end

always @ (posedge clk_b)
begin
// Port B READ
if (!rd_b)
q_b <= mem1[addr_b];
else
q_b <= 8'bzz;
end
endmodule