基于FPGA的VGA显示的设计程序

Answer 1

//module : VGA_controller.v

module VGA_controller(
// Host Side
iRed,
iGreen,
iBlue,
oAddress,
busy,
// VGA Side
oVGA_R,
oVGA_G,
oVGA_B,
oVGA_H_SYNC,
oVGA_V_SYNC,
oVGA_SYNC,
oVGA_BLANK,
oVGA_CLOCK,
// Control Signal
iCLK,
iRST_N );

// Horizontal Parameter ( Pixel )

parameter H_SYNC_CYC = 120;
parameter H_SYNC_BACK = 61+3;
parameter H_SYNC_ACT = 800; // 806
parameter H_SYNC_FRONT= 53+3;
parameter H_SYNC_TOTAL= 1040;
// Virtical Parameter ( Line )
parameter V_SYNC_CYC = 6;
parameter V_SYNC_BACK = 21+2;
parameter V_SYNC_ACT = 600; // 604
parameter V_SYNC_FRONT= 35+2;
parameter V_SYNC_TOTAL= 666;
// Start Offset
parameter X_START = H_SYNC_CYC+H_SYNC_BACK;
parameter Y_START = V_SYNC_CYC+V_SYNC_BACK;

// Host Side
output reg [13:0] oAddress;
input [7:0] iRed;
input [7:0] iGreen;
input [7:0] iBlue;
input busy; //modify 2011.1.18
// VGA Side
output [9:0] oVGA_R;
output [9:0] oVGA_G;
output [9:0] oVGA_B;
output reg oVGA_H_SYNC;
output reg oVGA_V_SYNC;
output oVGA_SYNC;
output oVGA_BLANK;
output oVGA_CLOCK;
// Control Signal
input iCLK;
input iRST_N;

// Internal Registers and Wires
reg [9:0] H_Cont;
reg [9:0] V_Cont;
reg [7:0] Cur_Color_R;
reg [7:0] Cur_Color_G;
reg [7:0] Cur_Color_B;

assign oVGA_BLANK = oVGA_H_SYNC & oVGA_V_SYNC;
assign oVGA_SYNC = 1'b0;
assign oVGA_CLOCK = iCLK;

//output RGB
assign oVGA_R = (H_Cont>=X_START && H_Cont<X_START+H_SYNC_ACT &&
V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )
?{2'b00,Cur_Color_R}:0;
assign oVGA_G = (H_Cont>=X_START && H_Cont<X_START+H_SYNC_ACT &&
V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )
?{2'b00,Cur_Color_G}:0;
assign oVGA_B = (H_Cont>=X_START && H_Cont<X_START+H_SYNC_ACT &&
V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )
?{2'b00,Cur_Color_B}:0;

// Pixel Address Generator
wire [9:0] posx;
wire [9:0] posy;
assign posx=H_Cont-X_START;
assign posy=V_Cont-Y_START;
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
oAddress <= 0;
end
else
begin
if( H_Cont>=X_START && H_Cont<X_START+H_SYNC_ACT &&
V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT && !busy) begin
oAddress <=posy*H_SYNC_ACT+posx;
end
else oAddress <= oAddress;
end
end

// Cursor Generator
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
Cur_Color_R <= 0;
Cur_Color_G <= 0;
Cur_Color_B <= 0;
end
else

begin
if( H_Cont>=X_START && H_Cont<X_START+H_SYNC_ACT&&
V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )
begin
Cur_Color_R <= iRed;
Cur_Color_G <= iGreen;
Cur_Color_B <= iBlue;
end
else
begin
Cur_Color_R <= Cur_Color_R;
Cur_Color_G <= Cur_Color_G;
Cur_Color_B <= Cur_Color_B;
end
end

end

// H_Sync Generator, Ref. 50 MHz Clock
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
H_Cont <= 0;
oVGA_H_SYNC <= 0;
end
else
begin
// H_Sync Counter
if( H_Cont < H_SYNC_TOTAL )
H_Cont <= H_Cont+1;
else
H_Cont <= 0;
// H_Sync Generator
if( H_Cont < H_SYNC_CYC )
oVGA_H_SYNC <= 0;
else
oVGA_H_SYNC <= 1;
end
end

// V_Sync Generator, Ref. H_Sync
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
V_Cont <= 0;
oVGA_V_SYNC <= 0;
end
else
begin
// When H_Sync Re-start
if(H_Cont==0)
begin
// V_Sync Counter
if( V_Cont < V_SYNC_TOTAL )
V_Cont <= V_Cont+1;
else
V_Cont <= 0;
// V_Sync Generator
if( V_Cont < V_SYNC_CYC )
oVGA_V_SYNC <= 0;
else
oVGA_V_SYNC <= 1;
end
end
end

endmodule