用VHDL设计一个计数器 代解释说明

Question

用VHDL设计一个计数器 代解释说明

Answer 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity cnt is
port(clk,contrl:in std_logic;
dout:out std_logic_vector(3 downto 0）);
end entity cnt;

architecture art of cnt is
signal Q :std_logic_vector(3 downto 0);
begin

process(clk)
begin
if clk'event and clk='1' then
Q <= Q + '1'; --四位加法计数器
end if;

dout <= Q;

end art;