USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter4 is
port
(
clk : in std_logic;
load : in std_logic;
clr : in std_logic;
up_down: in std_logic;
DIN : in std_logic_vector(3 downto 0);
DOUT : out std_logic_vector(3 downto 0);
c : out std_logic
);
end counter4;
architecture rt1 of counter4 is
signal clk_1Hz:std_logic;
signal data_r:std_logic_vector(3 downto 0);
component frediv
port
(
clk :in std_logic;
clkout:out std_logic
);
end component;
begin
U1:frediv port map(clk,clk_1Hz);
DOUT <= data_r;
process(clk_1Hz,load,clr,up_down,DIN)
begin
if clr = '1' then
data_r <= "0000";
elsif load = '1' then
data_r <= DIN;
else if clk_1Hz'event and clk_1Hz = '1' then
if up_down = '1' then
if data_r = "1111" then
c <= '0';
data_r <= "0000";
else
data_r <= data_r + 1;
c<= '1';
end if;
else
if data_r = "0000" then
c <= '0';
data_r <= "1111";
else
data_r <= data_r - 1;
c<= '1';
end if;
end if;
end if;
end if;
end process;
end rt1;追问
不对哦,有错误,看图
追答LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter4 is
port
(
clk : in std_logic;
load : in std_logic;
clr : in std_logic;
up_down: in std_logic;
DIN : in std_logic_vector(3 downto 0);
DOUT : out std_logic_vector(3 downto 0);
c : out std_logic
);
end counter4;
architecture rt1 of counter4 is
signal data_r:std_logic_vector(3 downto 0);
begin
DOUT <= data_r;
process(clk,load,clr,up_down,DIN)
begin
if clr = '1' then
data_r <= "0000";
elsif load = '1' then
data_r <= DIN;
else if clk'event and clk = '1' then
if up_down = '1' then
if data_r = "1111" then
c <= '0';
data_r <= "0000";
else
data_r <= data_r + 1;
c<= '1';
end if;
else
if data_r = "0000" then
c <= '0';
data_r <= "1111";
else
data_r <= data_r - 1;
c<= '1';
end if;
end if;
end if;
end if;
end process;
end rt1;
之前写的，中间调用了一个子程序，忘了删了，现在好了。
