第1个回答 2009-06-01
http://book.idoican.com.cn/detail/DefaultView.aspx?BookId=m20071222m003w011095
中的第十章
中的第十章
参考资料：《工程建设项目管理基础教程》
第2个回答 2009-05-31
Abstract: AT89C51 is a flicker with 4K byte erasable programmable read-only memory (FPEROM) Falsh Programmable and Erasable Read Only Memory) of the low-voltage, high-performance digital microprocessors CMOS8, commonly known as single-chip microcomputer.
The device ATMEL manufacture high-density nonvolatile memory technology with industry-standard MCS-51 instruction set and pin compatible output. Owing to the multi-purpose 8-bit CPU and flash memory chips in a single portfolio, ATMEL The AT89C51 is a high-performance microcontrollers, embedded control systems for many provides a flexible and inexpensive program.
1. Key Features:
And MCS-51 compatible
Programmable 4K bytes Flash Memory
Life expectancy: 1000 write / wipe cycle
Data retention time: 10 years
Static work of the whole: 0Hz-24Hz
Three-level Program Memory Lock
128 * 8-bit Internal RAM
32 programmable I / O lines
Two 16-bit timer / counter
5 interrupt sources
Programmable Serial Channel
Low-power idle and power-down mode
Chip oscillator and clock circuitry
2. Pin Description:
VCC: power supply voltage.
GND: Ground.
P0 I: P0 port for an 8-bit open drain bi-directional level I / O port, each pin can absorb current 8TTL door. When the pin P1 the first time I write 1, is defined as the high impedance input. P0 procedures can be used for external data memory, which can be defined as data / address of the eighth. In FIASH programming, P0 port input as the original code, when FIASH when to check, P0 output of the original code, this time to be pushed outside P0.
P1 port: P1 port is an internal pull-up resistor to provide the 8-bit bi-directional I / O port, P1 port output buffer to receive current 4TTL door. I write P1 pin 1, the internal pull-high, can be used as input, P1 I was outside when the drop-down low, the output current, which is due to internal reasons pull. FLASH programming and check in time, P1 as the eighth address I receive.
P2 port: P2 mouth to an internal pull-up resistor 8-bit bi-directional I / O port, P2 I receive buffers, the output current of 4 TTL gate, when the P2 I was writing "1", the pin was inside the push pull-up resistor, and as an input. And therefore as a type, P2 I was outside of the pin down, the output current. This is due to internal reasons pull. P2 I, when used in external program memory or 16-bit addresses to access external data memory when, P2 I address the high-output 8. In the given address "1" when using the internal pull-advantage, when eight of the external data memory read and write address when, P2 I output the contents of special function registers. P2 I check in the FLASH programming and high-eight hours to receive the address signals and control signals.
P3 I: P3 port is 8-pin with internal pull-up resistor on the bi-directional I / O port to receive the output current of 4 TTL gate. P3 When I write "1", they were for internal pull-high, and used as input. As input, as the external pull-down low, P3 will output current I (ILL) This is because the pull of the reason.
P3 port can also be used as a number of special features AT89C51 mouth, the following table:
Functional I-pin options
P3.0 RXD (serial input)
P3.1 TXD (serial output port)
P3.2 / INT0 (external interrupt 0)
P3.3 / INT1 (external interrupt 1)
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 / WR (external data memory write strobe)
P3.7 / RD (external data memory read strobe)
P3 mouth at the same time flashing check programming and programming a number of control signals to receive.
RST: Reset input. When the oscillator device reset, the RST pin to maintain the high level of two machine cycle time.
ALE / PROG: When access to external memory, the address latch of the output level to allow for the latch status of the address byte. FLASH programming in the period, this pin for input pulse programming. In peacetime, ALE client to change the frequency of cycle positive pulse output signal, the frequency of the oscillator frequency of 1 / 6. Therefore it can be used as a pulse output to the outside or for the purpose from time to time. However, it should be noted that: When used as external data memory, it will skip one ALE pulse. If you want to prohibit the output of ALE can be SFR8EH home address 0. At this point, ALE is only in the implementation of MOVX, MOVC instruction is the only role of ALE. In addition, the pin was pushed up slightly. If the microprocessor in the implementation of the state of the external ALE prohibited invalid home.
/ PSEN: external program memory of the selected signal. By the external program memory access refers to the period, twice each machine cycle / PSEN effective. However, when access to external data memory, these two effective / PSEN signal will not occur.
/ EA / VPP: When / EA to maintain low-level, then during this period the external program memory (0000H-FFFFH), regardless of whether there is an internal program memory. Note 1 encryption method, / EA will be locked to the internal RESET; when / EA to maintain high-end, the said internal program memory. FLASH programming in the period, this pin is also used to exert power 12V programming (VPP).
XTAL1: reverse oscillation amplifier input and the work of the internal clock circuit input.
XTAL2: Output from the oscillator reverse.
3. Oscillator characteristics:
XTAL1 and XTAL2 are the reverse of the input and output amplifier. The amplifier can be configured to reverse-chip oscillator. Oscillation oscillation crystals and ceramics can be used. If an external clock source drive the device, XTAL2 should not take. Than to the internal clock signal input through a second sub-frequency flip-flop, so the external clock signal pulse width without any request, but must ensure that the high-low pulse width requirements.
4. Chip erase:
PEROM whole array and three lock-bit erase power by the right combination of control signals, and maintain at a low level ALE pin 10ms to complete. Rub in the chip operation, code arrays were to write "1" and stored in any non-null byte to be programmed to repeat the past, the operation must be executed.
In addition, AT89C51 has a steady-state logic, can be in the low to zero frequency under the conditions of static logic, supports two software selectable power-down mode. In idle mode, CPU to stop working. However, RAM, timers, counters, serial port and interrupt system are still working. In power-down mode, to preserve the contents of RAM and freeze oscillator, the prohibition of the use of other chip functions until the next reset date hardware.
Click here to download PDF English AT89C51 chips document
51 single-chip, many novice users will have this problem: AT89S51 what? Books and online tutorials can 8051,89 C51, etc. are! Have heard of 89S51? !
Here, beginners would like to clarify the practical use of single-chip, a product concept, MCS-51 single-chip companies in the United States INTE products in 1980, the typical products of 8031 (there is no internal program memory, the actual use of the market has been out), 8051 (chip HMOS, power consumption is 630mW, the 89C51 5 times, the actual use has been eliminated) and the 8751 general products, such as a date, MCS-51 compatible microcontroller core series is still is the application of the mainstream products (such as the current popular 89S51, the 89C51 has been shutdown, etc.), colleges and universities and professional schools and the training materials are still MCS-51 single-chip, as the theoretical foundation for learning.
Some literature even refers to the 8051 series MCS-51 microcontroller, 8051 is an early representative of the most typical, as the MCS-51 single-chip far-reaching impact, many companies have launched a series of single-chip-compatible, that is, MCS -51 kernel has actually become a standard 8-bit microcontroller.
51 other companies and single-chip products are compatible with MCS-51 core products to. Section of the same procedures, in all single-chip hardware manufacturers to run on the results are the same, such as the ATMEL's 89C51 (discontinued), 89S51, PHILIPS (Philips), and WINBOND (Winbond), etc., we have often said that the 89C51 production refers to the ATMEL Corporation AT89C51 single-chip, at the same time the basis of the original number of enhanced features such as clock, better by the Flash (program memory contents can be rewritten at least 1000 times) memory check with the original ROM (one-time write), AT89C51 performance relative to 8051 has been regarded as a very superior.
However, in regard to the market, 89C51 single-chip microcomputer PIC camp has been the challenge, 89C51 is the most fatal flaw does not support ISP (Online Update) function, the function must be coupled with new features such as ISP can be a better continuation of the legend of MCS-51 . 89S51 is against this background that replace the 89C51, but now, 89S51 current practical application has become the new darling of the market, as the market share of the first production Atmel currently has AT89C51, will be used to replace AT89S51. 89S51 in technology improvements, 89S51 using 0.35 new technology, cost reduction, but also enhanced, more competitive. Can 89SXX under 89CXX compatible chips such as 51 series. At the same time, Atmel no longer accept orders 89CXX, everyone in the market to see the actual 89C51 are Atmel massive pre-production to inventory.
89S51 increase compared with the 89C51 new features include:
- A lot of new features, performance have been greatly upgraded, the price will remain basically unchanged, and even lower than the 89C51!
- ISP online programming feature, this feature has the advantage of being rewritten in the single-chip program memory chips do not need to spin-off from the work environment. Is a powerful easy-to-use functions.
- Operating frequency is 33MHz, we all know the limits of operating frequency 89C51 only 24M, that is to say, the work of a higher frequency of S51, which has a faster computing speed.
- With duplex UART serial channel.
- Internal integrated watchdog timer, are no longer required as the 89C51 module as an external watchdog timer circuit.
- Dual data pointer.
- Power-down logo.
- A new encryption algorithm, which allows for the decryption of 89S51 into impossible, the confidentiality of the procedure greatly enhanced, so that effective protection of intellectual property rights can not be violated.
- Compatibility: fully compatible with the next 51 characters of all products. 8051,89 C51, etc. For example, early MCS-51 compatible products. This means that all the textbooks, Web tutorial on the procedure (whether used in textbooks or the 89C51 single-chip is a 8051 or MCS-51, etc.), the same as in the 89S51 can be run as usual, and this is the so-called backwards compatibility.
AT89S51 example watchdog procedures are as follows:
AJMP MAIN
MAIN:
; Start watchdog
Mov 0A6H, # 01EH; first sent 1E
Mov 0A6H, # 0E1H; evacuation E1
; Main *********************************************** *************
;************************************************* *****************
START:
ACALL WDT; watchdog reset subroutine call
AJMP START
; Main *********************************************** *************
;************************************************* *****************
; Reset watchdog subroutine
WDT:
Mov 0A6H, # 01EH; first sent 1E
Mov 0A6H, # 0E1H; evacuation E1
RET
END
Note:
1. 89S51 watchdog must be activated, only to start after the procedure. Therefore, we must ensure that CPU have a reliable power-on reset.
Watchdog can not work otherwise.
2. CPU watchdog is used in the crystal. Vibration in the crystal when stopping watchdog also invalid.
3. 89S51 only 14 counters. 16,383 machines in the cycle must have at least one for dog. And this time is solid
Set, can not be changed. When the crystal is 12M per 16 ms to be a for dog.
-------------------
摘要: AT89C51是一种带4K字节闪烁可编程可擦除只读存储器（FPEROM)Falsh Programmable and Erasable Read Only Memory）的低电压，高性能CMOS8位微处理器，俗称单片机。
该器件采用ATMEL高密度非易失存储器制造技术制造，与工业标准的MCS-51指令集和输出管脚相兼容。由于将多功能8位CPU和闪烁存储器组合在单个芯片中，ATMEL的AT89C51是一种高效微控制器，为很多嵌入式控制系统提供了一种灵活性高且价廉的方案。
1．主要特性：
·与MCS-51 兼容
·4K字节可编程闪烁存储器
寿命：1000写/擦循环
数据保留时间：10年
·全静态工作：0Hz-24Hz
·三级程序存储器锁定
·128*8位内部RAM
·32可编程I/O线
·两个16位定时器/计数器
·5个中断源
·可编程串行通道
·低功耗的闲置和掉电模式
·片内振荡器和时钟电路
2．管脚说明：
VCC：供电电压。
GND：接地。
P0口：P0口为一个8位漏级开路双向I/O口，每脚可吸收8TTL门电流。当P1口的管脚第一次写1时，被定义为高阻输入。P0能够用于外部程序数据存储器，它可以被定义为数据/地址的第八位。在FIASH编程时，P0 口作为原码输入口，当FIASH进行校验时，P0输出原码，此时P0外部必须被拉高。
P1口：P1口是一个内部提供上拉电阻的8位双向I/O口，P1口缓冲器能接收输出4TTL门电流。P1口管脚写入1后，被内部上拉为高，可用作输入，P1口被外部下拉为低电平时，将输出电流，这是由于内部上拉的缘故。在FLASH编程和校验时，P1口作为第八位地址接收。
P2口：P2口为一个内部上拉电阻的8位双向I/O口，P2口缓冲器可接收，输出4个TTL门电流，当P2口被写“1”时，其管脚被内部上拉电阻拉高，且作为输入。并因此作为输入时，P2口的管脚被外部拉低，将输出电流。这是由于内部上拉的缘故。P2口当用于外部程序存储器或16位地址外部数据存储器进行存取时，P2口输出地址的高八位。在给出地址“1”时，它利用内部上拉优势，当对外部八位地址数据存储器进行读写时，P2口输出其特殊功能寄存器的内容。P2口在FLASH编程和校验时接收高八位地址信号和控制信号。
P3口：P3口管脚是8个带内部上拉电阻的双向I/O口，可接收输出4个TTL门电流。当P3口写入“1”后，它们被内部上拉为高电平，并用作输入。作为输入，由于外部下拉为低电平，P3口将输出电流（ILL）这是由于上拉的缘故。
P3口也可作为AT89C51的一些特殊功能口，如下表所示：
口管脚 备选功能
P3.0 RXD（串行输入口）
P3.1 TXD（串行输出口）
P3.2 /INT0（外部中断0）
P3.3 /INT1（外部中断1）
P3.4 T0（记时器0外部输入）
P3.5 T1（记时器1外部输入）
P3.6 /WR（外部数据存储器写选通）
P3.7 /RD（外部数据存储器读选通）
P3口同时为闪烁编程和编程校验接收一些控制信号。
RST：复位输入。当振荡器复位器件时，要保持RST脚两个机器周期的高电平时间。
ALE/PROG：当访问外部存储器时，地址锁存允许的输出电平用于锁存地址的地位字节。在FLASH编程期间，此引脚用于输入编程脉冲。在平时，ALE端以不变的频率周期输出正脉冲信号，此频率为振荡器频率的1/6。因此它可用作对外部输出的脉冲或用于定时目的。然而要注意的是：每当用作外部数据存储器时，将跳过一个ALE脉冲。如想禁止ALE的输出可在SFR8EH地址上置0。此时， ALE只有在执行MOVX，MOVC指令是ALE才起作用。另外，该引脚被略微拉高。如果微处理器在外部执行状态ALE禁止，置位无效。
/PSEN：外部程序存储器的选通信号。在由外部程序存储器取指期间，每个机器周期两次/PSEN有效。但在访问外部数据存储器时，这两次有效的/PSEN信号将不出现。
/EA/VPP：当/EA保持低电平时，则在此期间外部程序存储器（0000H-FFFFH），不管是否有内部程序存储器。注意加密方式1时，/EA将内部锁定为RESET；当/EA端保持高电平时，此间内部程序存储器。在FLASH编程期间，此引脚也用于施加12V编程电源（VPP）。
XTAL1：反向振荡放大器的输入及内部时钟工作电路的输入。
XTAL2：来自反向振荡器的输出。
3．振荡器特性：
XTAL1和XTAL2分别为反向放大器的输入和输出。该反向放大器可以配置为片内振荡器。石晶振荡和陶瓷振荡均可采用。如采用外部时钟源驱动器件，XTAL2应不接。有余输入至内部时钟信号要通过一个二分频触发器，因此对外部时钟信号的脉宽无任何要求，但必须保证脉冲的高低电平要求的宽度。
4．芯片擦除：
整个PEROM阵列和三个锁定位的电擦除可通过正确的控制信号组合，并保持ALE管脚处于低电平10ms 来完成。在芯片擦操作中，代码阵列全被写“1”且在任何非空存储字节被重复编程以前，该操作必须被执行。
此外，AT89C51设有稳态逻辑，可以在低到零频率的条件下静态逻辑，支持两种软件可选的掉电模式。在闲置模式下，CPU停止工作。但RAM，定时器，计数器，串口和中断系统仍在工作。在掉电模式下，保存RAM的内容并且冻结振荡器，禁止所用其他芯片功能，直到下一个硬件复位为止。
点击这里可以下载AT89C51芯片的英文PDF文档
很多初学51单片机的网友会有这样的问题：AT89S51是什么?书上和网络教程上可都是8051，89C51等！没听说过有89S51 ？！
这里，初学者要澄清单片机实际使用方面的一个产品概念，MCS-51单片机是美国INTE公司于1980年推出的产品，典型产品有 8031（内部没有程序存储器，实际使用方面已经被市场淘汰）、8051（芯片采用HMOS，功耗是630mW，是89C51的5倍，实际使用方面已经被市场淘汰）和8751等通用产品，一直到现在， MCS-51内核系列兼容的单片机仍是应用的主流产品（比如目前流行的89S51、已经停产的89C51等），各高校及专业学校的培训教材仍与MCS-51单片机作为代表进行理论基础学习。
有些文献甚至也将8051泛指MCS-51系列单片机，8051是早期的最典型的代表作，由于MCS-51单片机影响极深远，许多公司都推出了兼容系列单片机，就是说MCS-51内核实际上已经成为一个8位单片机的标准。
其他的公司的51单片机产品都是和MCS-51内核兼容的产品而以。同样的一段程序，在各个单片机厂家的硬件上运行的结果都是一样的，如ATMEL的89C51（已经停产）、89S51， PHILIPS（菲利浦），和WINBOND（华邦）等，我们常说的已经停产的89C51指的是ATMEL公司的 AT89C51单片机，同时是在原基础上增强了许多特性，如时钟，更优秀的是由Flash（程序存储器的内容至少可以改写1000次）存储器取带了原来的ROM（一次性写入），AT89C51的性能相对于8051已经算是非常优越的了。
不过在市场化方面，89C51受到了PIC单片机阵营的挑战，89C51最致命的缺陷在于不支持ISP（在线更新程序）功能，必须加上ISP功能等新功能才能更好延续MCS-51的传奇。89S51就是在这样的背景下取代89C51的，现在，89S51目前已经成为了实际应用市场上新的宠儿，作为市场占有率第一的Atmel目前公司已经停产AT89C51，将用AT89S51代替。89S51在工艺上进行了改进，89S51采用0.35新工艺，成本降低,而且将功能提升,增加了竞争力。89SXX可以像下兼容89CXX等51系列芯片。同时，Atmel不再接受89CXX的定单，大家在市场上见到的89C51实际都是Atmel前期生产的巨量库存而以。
89S51相对于89C51增加的新功能包括：
-- 新增加很多功能，性能有了较大提升，价格却基本不变，甚至比89C51更低！
-- ISP在线编程功能，这个功能的优势在于改写单片机存储器内的程序不需要把芯片从工作环境中剥离。是一个强大易用的功能。
-- 工作频率为33MHz，大家都知道89C51的极限工作频率只有24M，就是说S51具有更高工作频率，从而具有了更快的计算速度。
-- 具有双工UART串行通道。
-- 内部集成看门狗计时器，不再需要像89C51那样外接看门狗计时器单元电路。
-- 双数据指示器。
-- 电源关闭标识。
-- 全新的加密算法，这使得对于89S51的解密变为不可能，程序的保密性大大加强，这样就可以有效的保护知识产权不被侵犯。
-- 兼容性方面：向下完全兼容51全部字系列产品。比如8051、89C51等等早期MCS-51兼容产品。也就是说所有教科书、网络教程上的程序（不论教科书上采用的单片机是8051还是89C51还是MCS-51等等），在89S51上一样可以照常运行，这就是所谓的向下兼容。
AT89S51看门狗程序例子如下：
AJMP MAIN
MAIN:
;启动看门狗
Mov 0A6H,#01EH ;先送1E
Mov 0A6H,#0E1H ;后送E1
;主程序************************************************************
;******************************************************************
START:
ACALL WDT ;调用复位看门狗子程序
AJMP START
;主程序************************************************************
;******************************************************************
;复位看门狗子程序
WDT:
Mov 0A6H,#01EH ;先送1E
Mov 0A6H,#0E1H ;后送E1
RET
END
注意事项：
1． 89S51的看门狗必须由程序激活后才开始工作。所以必须保证CPU有可靠的上电复位。
否则看门狗也无法工作。
2． 看门狗使用的是CPU的晶振。在晶振停振的时候看门狗也无效。
3． 89S51只有14位计数器。在16383个机器周期内必须至少喂狗一次。而且这个时间是固
定的，无法更改。当晶振为12M时每16个毫秒需喂狗一次。本回答被网友采纳
The device ATMEL manufacture high-density nonvolatile memory technology with industry-standard MCS-51 instruction set and pin compatible output. Owing to the multi-purpose 8-bit CPU and flash memory chips in a single portfolio, ATMEL The AT89C51 is a high-performance microcontrollers, embedded control systems for many provides a flexible and inexpensive program.
1. Key Features:
And MCS-51 compatible
Programmable 4K bytes Flash Memory
Life expectancy: 1000 write / wipe cycle
Data retention time: 10 years
Static work of the whole: 0Hz-24Hz
Three-level Program Memory Lock
128 * 8-bit Internal RAM
32 programmable I / O lines
Two 16-bit timer / counter
5 interrupt sources
Programmable Serial Channel
Low-power idle and power-down mode
Chip oscillator and clock circuitry
2. Pin Description:
VCC: power supply voltage.
GND: Ground.
P0 I: P0 port for an 8-bit open drain bi-directional level I / O port, each pin can absorb current 8TTL door. When the pin P1 the first time I write 1, is defined as the high impedance input. P0 procedures can be used for external data memory, which can be defined as data / address of the eighth. In FIASH programming, P0 port input as the original code, when FIASH when to check, P0 output of the original code, this time to be pushed outside P0.
P1 port: P1 port is an internal pull-up resistor to provide the 8-bit bi-directional I / O port, P1 port output buffer to receive current 4TTL door. I write P1 pin 1, the internal pull-high, can be used as input, P1 I was outside when the drop-down low, the output current, which is due to internal reasons pull. FLASH programming and check in time, P1 as the eighth address I receive.
P2 port: P2 mouth to an internal pull-up resistor 8-bit bi-directional I / O port, P2 I receive buffers, the output current of 4 TTL gate, when the P2 I was writing "1", the pin was inside the push pull-up resistor, and as an input. And therefore as a type, P2 I was outside of the pin down, the output current. This is due to internal reasons pull. P2 I, when used in external program memory or 16-bit addresses to access external data memory when, P2 I address the high-output 8. In the given address "1" when using the internal pull-advantage, when eight of the external data memory read and write address when, P2 I output the contents of special function registers. P2 I check in the FLASH programming and high-eight hours to receive the address signals and control signals.
P3 I: P3 port is 8-pin with internal pull-up resistor on the bi-directional I / O port to receive the output current of 4 TTL gate. P3 When I write "1", they were for internal pull-high, and used as input. As input, as the external pull-down low, P3 will output current I (ILL) This is because the pull of the reason.
P3 port can also be used as a number of special features AT89C51 mouth, the following table:
Functional I-pin options
P3.0 RXD (serial input)
P3.1 TXD (serial output port)
P3.2 / INT0 (external interrupt 0)
P3.3 / INT1 (external interrupt 1)
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 / WR (external data memory write strobe)
P3.7 / RD (external data memory read strobe)
P3 mouth at the same time flashing check programming and programming a number of control signals to receive.
RST: Reset input. When the oscillator device reset, the RST pin to maintain the high level of two machine cycle time.
ALE / PROG: When access to external memory, the address latch of the output level to allow for the latch status of the address byte. FLASH programming in the period, this pin for input pulse programming. In peacetime, ALE client to change the frequency of cycle positive pulse output signal, the frequency of the oscillator frequency of 1 / 6. Therefore it can be used as a pulse output to the outside or for the purpose from time to time. However, it should be noted that: When used as external data memory, it will skip one ALE pulse. If you want to prohibit the output of ALE can be SFR8EH home address 0. At this point, ALE is only in the implementation of MOVX, MOVC instruction is the only role of ALE. In addition, the pin was pushed up slightly. If the microprocessor in the implementation of the state of the external ALE prohibited invalid home.
/ PSEN: external program memory of the selected signal. By the external program memory access refers to the period, twice each machine cycle / PSEN effective. However, when access to external data memory, these two effective / PSEN signal will not occur.
/ EA / VPP: When / EA to maintain low-level, then during this period the external program memory (0000H-FFFFH), regardless of whether there is an internal program memory. Note 1 encryption method, / EA will be locked to the internal RESET; when / EA to maintain high-end, the said internal program memory. FLASH programming in the period, this pin is also used to exert power 12V programming (VPP).
XTAL1: reverse oscillation amplifier input and the work of the internal clock circuit input.
XTAL2: Output from the oscillator reverse.
3. Oscillator characteristics:
XTAL1 and XTAL2 are the reverse of the input and output amplifier. The amplifier can be configured to reverse-chip oscillator. Oscillation oscillation crystals and ceramics can be used. If an external clock source drive the device, XTAL2 should not take. Than to the internal clock signal input through a second sub-frequency flip-flop, so the external clock signal pulse width without any request, but must ensure that the high-low pulse width requirements.
4. Chip erase:
PEROM whole array and three lock-bit erase power by the right combination of control signals, and maintain at a low level ALE pin 10ms to complete. Rub in the chip operation, code arrays were to write "1" and stored in any non-null byte to be programmed to repeat the past, the operation must be executed.
In addition, AT89C51 has a steady-state logic, can be in the low to zero frequency under the conditions of static logic, supports two software selectable power-down mode. In idle mode, CPU to stop working. However, RAM, timers, counters, serial port and interrupt system are still working. In power-down mode, to preserve the contents of RAM and freeze oscillator, the prohibition of the use of other chip functions until the next reset date hardware.
Click here to download PDF English AT89C51 chips document
51 single-chip, many novice users will have this problem: AT89S51 what? Books and online tutorials can 8051,89 C51, etc. are! Have heard of 89S51? !
Here, beginners would like to clarify the practical use of single-chip, a product concept, MCS-51 single-chip companies in the United States INTE products in 1980, the typical products of 8031 (there is no internal program memory, the actual use of the market has been out), 8051 (chip HMOS, power consumption is 630mW, the 89C51 5 times, the actual use has been eliminated) and the 8751 general products, such as a date, MCS-51 compatible microcontroller core series is still is the application of the mainstream products (such as the current popular 89S51, the 89C51 has been shutdown, etc.), colleges and universities and professional schools and the training materials are still MCS-51 single-chip, as the theoretical foundation for learning.
Some literature even refers to the 8051 series MCS-51 microcontroller, 8051 is an early representative of the most typical, as the MCS-51 single-chip far-reaching impact, many companies have launched a series of single-chip-compatible, that is, MCS -51 kernel has actually become a standard 8-bit microcontroller.
51 other companies and single-chip products are compatible with MCS-51 core products to. Section of the same procedures, in all single-chip hardware manufacturers to run on the results are the same, such as the ATMEL's 89C51 (discontinued), 89S51, PHILIPS (Philips), and WINBOND (Winbond), etc., we have often said that the 89C51 production refers to the ATMEL Corporation AT89C51 single-chip, at the same time the basis of the original number of enhanced features such as clock, better by the Flash (program memory contents can be rewritten at least 1000 times) memory check with the original ROM (one-time write), AT89C51 performance relative to 8051 has been regarded as a very superior.
However, in regard to the market, 89C51 single-chip microcomputer PIC camp has been the challenge, 89C51 is the most fatal flaw does not support ISP (Online Update) function, the function must be coupled with new features such as ISP can be a better continuation of the legend of MCS-51 . 89S51 is against this background that replace the 89C51, but now, 89S51 current practical application has become the new darling of the market, as the market share of the first production Atmel currently has AT89C51, will be used to replace AT89S51. 89S51 in technology improvements, 89S51 using 0.35 new technology, cost reduction, but also enhanced, more competitive. Can 89SXX under 89CXX compatible chips such as 51 series. At the same time, Atmel no longer accept orders 89CXX, everyone in the market to see the actual 89C51 are Atmel massive pre-production to inventory.
89S51 increase compared with the 89C51 new features include:
- A lot of new features, performance have been greatly upgraded, the price will remain basically unchanged, and even lower than the 89C51!
- ISP online programming feature, this feature has the advantage of being rewritten in the single-chip program memory chips do not need to spin-off from the work environment. Is a powerful easy-to-use functions.
- Operating frequency is 33MHz, we all know the limits of operating frequency 89C51 only 24M, that is to say, the work of a higher frequency of S51, which has a faster computing speed.
- With duplex UART serial channel.
- Internal integrated watchdog timer, are no longer required as the 89C51 module as an external watchdog timer circuit.
- Dual data pointer.
- Power-down logo.
- A new encryption algorithm, which allows for the decryption of 89S51 into impossible, the confidentiality of the procedure greatly enhanced, so that effective protection of intellectual property rights can not be violated.
- Compatibility: fully compatible with the next 51 characters of all products. 8051,89 C51, etc. For example, early MCS-51 compatible products. This means that all the textbooks, Web tutorial on the procedure (whether used in textbooks or the 89C51 single-chip is a 8051 or MCS-51, etc.), the same as in the 89S51 can be run as usual, and this is the so-called backwards compatibility.
AT89S51 example watchdog procedures are as follows:
AJMP MAIN
MAIN:
; Start watchdog
Mov 0A6H, # 01EH; first sent 1E
Mov 0A6H, # 0E1H; evacuation E1
; Main *********************************************** *************
;************************************************* *****************
START:
ACALL WDT; watchdog reset subroutine call
AJMP START
; Main *********************************************** *************
;************************************************* *****************
; Reset watchdog subroutine
WDT:
Mov 0A6H, # 01EH; first sent 1E
Mov 0A6H, # 0E1H; evacuation E1
RET
END
Note:
1. 89S51 watchdog must be activated, only to start after the procedure. Therefore, we must ensure that CPU have a reliable power-on reset.
Watchdog can not work otherwise.
2. CPU watchdog is used in the crystal. Vibration in the crystal when stopping watchdog also invalid.
3. 89S51 only 14 counters. 16,383 machines in the cycle must have at least one for dog. And this time is solid
Set, can not be changed. When the crystal is 12M per 16 ms to be a for dog.
-------------------
摘要: AT89C51是一种带4K字节闪烁可编程可擦除只读存储器（FPEROM)Falsh Programmable and Erasable Read Only Memory）的低电压，高性能CMOS8位微处理器，俗称单片机。
该器件采用ATMEL高密度非易失存储器制造技术制造，与工业标准的MCS-51指令集和输出管脚相兼容。由于将多功能8位CPU和闪烁存储器组合在单个芯片中，ATMEL的AT89C51是一种高效微控制器，为很多嵌入式控制系统提供了一种灵活性高且价廉的方案。
1．主要特性：
·与MCS-51 兼容
·4K字节可编程闪烁存储器
寿命：1000写/擦循环
数据保留时间：10年
·全静态工作：0Hz-24Hz
·三级程序存储器锁定
·128*8位内部RAM
·32可编程I/O线
·两个16位定时器/计数器
·5个中断源
·可编程串行通道
·低功耗的闲置和掉电模式
·片内振荡器和时钟电路
2．管脚说明：
VCC：供电电压。
GND：接地。
P0口：P0口为一个8位漏级开路双向I/O口，每脚可吸收8TTL门电流。当P1口的管脚第一次写1时，被定义为高阻输入。P0能够用于外部程序数据存储器，它可以被定义为数据/地址的第八位。在FIASH编程时，P0 口作为原码输入口，当FIASH进行校验时，P0输出原码，此时P0外部必须被拉高。
P1口：P1口是一个内部提供上拉电阻的8位双向I/O口，P1口缓冲器能接收输出4TTL门电流。P1口管脚写入1后，被内部上拉为高，可用作输入，P1口被外部下拉为低电平时，将输出电流，这是由于内部上拉的缘故。在FLASH编程和校验时，P1口作为第八位地址接收。
P2口：P2口为一个内部上拉电阻的8位双向I/O口，P2口缓冲器可接收，输出4个TTL门电流，当P2口被写“1”时，其管脚被内部上拉电阻拉高，且作为输入。并因此作为输入时，P2口的管脚被外部拉低，将输出电流。这是由于内部上拉的缘故。P2口当用于外部程序存储器或16位地址外部数据存储器进行存取时，P2口输出地址的高八位。在给出地址“1”时，它利用内部上拉优势，当对外部八位地址数据存储器进行读写时，P2口输出其特殊功能寄存器的内容。P2口在FLASH编程和校验时接收高八位地址信号和控制信号。
P3口：P3口管脚是8个带内部上拉电阻的双向I/O口，可接收输出4个TTL门电流。当P3口写入“1”后，它们被内部上拉为高电平，并用作输入。作为输入，由于外部下拉为低电平，P3口将输出电流（ILL）这是由于上拉的缘故。
P3口也可作为AT89C51的一些特殊功能口，如下表所示：
口管脚 备选功能
P3.0 RXD（串行输入口）
P3.1 TXD（串行输出口）
P3.2 /INT0（外部中断0）
P3.3 /INT1（外部中断1）
P3.4 T0（记时器0外部输入）
P3.5 T1（记时器1外部输入）
P3.6 /WR（外部数据存储器写选通）
P3.7 /RD（外部数据存储器读选通）
P3口同时为闪烁编程和编程校验接收一些控制信号。
RST：复位输入。当振荡器复位器件时，要保持RST脚两个机器周期的高电平时间。
ALE/PROG：当访问外部存储器时，地址锁存允许的输出电平用于锁存地址的地位字节。在FLASH编程期间，此引脚用于输入编程脉冲。在平时，ALE端以不变的频率周期输出正脉冲信号，此频率为振荡器频率的1/6。因此它可用作对外部输出的脉冲或用于定时目的。然而要注意的是：每当用作外部数据存储器时，将跳过一个ALE脉冲。如想禁止ALE的输出可在SFR8EH地址上置0。此时， ALE只有在执行MOVX，MOVC指令是ALE才起作用。另外，该引脚被略微拉高。如果微处理器在外部执行状态ALE禁止，置位无效。
/PSEN：外部程序存储器的选通信号。在由外部程序存储器取指期间，每个机器周期两次/PSEN有效。但在访问外部数据存储器时，这两次有效的/PSEN信号将不出现。
/EA/VPP：当/EA保持低电平时，则在此期间外部程序存储器（0000H-FFFFH），不管是否有内部程序存储器。注意加密方式1时，/EA将内部锁定为RESET；当/EA端保持高电平时，此间内部程序存储器。在FLASH编程期间，此引脚也用于施加12V编程电源（VPP）。
XTAL1：反向振荡放大器的输入及内部时钟工作电路的输入。
XTAL2：来自反向振荡器的输出。
3．振荡器特性：
XTAL1和XTAL2分别为反向放大器的输入和输出。该反向放大器可以配置为片内振荡器。石晶振荡和陶瓷振荡均可采用。如采用外部时钟源驱动器件，XTAL2应不接。有余输入至内部时钟信号要通过一个二分频触发器，因此对外部时钟信号的脉宽无任何要求，但必须保证脉冲的高低电平要求的宽度。
4．芯片擦除：
整个PEROM阵列和三个锁定位的电擦除可通过正确的控制信号组合，并保持ALE管脚处于低电平10ms 来完成。在芯片擦操作中，代码阵列全被写“1”且在任何非空存储字节被重复编程以前，该操作必须被执行。
此外，AT89C51设有稳态逻辑，可以在低到零频率的条件下静态逻辑，支持两种软件可选的掉电模式。在闲置模式下，CPU停止工作。但RAM，定时器，计数器，串口和中断系统仍在工作。在掉电模式下，保存RAM的内容并且冻结振荡器，禁止所用其他芯片功能，直到下一个硬件复位为止。
点击这里可以下载AT89C51芯片的英文PDF文档
很多初学51单片机的网友会有这样的问题：AT89S51是什么?书上和网络教程上可都是8051，89C51等！没听说过有89S51 ？！
这里，初学者要澄清单片机实际使用方面的一个产品概念，MCS-51单片机是美国INTE公司于1980年推出的产品，典型产品有 8031（内部没有程序存储器，实际使用方面已经被市场淘汰）、8051（芯片采用HMOS，功耗是630mW，是89C51的5倍，实际使用方面已经被市场淘汰）和8751等通用产品，一直到现在， MCS-51内核系列兼容的单片机仍是应用的主流产品（比如目前流行的89S51、已经停产的89C51等），各高校及专业学校的培训教材仍与MCS-51单片机作为代表进行理论基础学习。
有些文献甚至也将8051泛指MCS-51系列单片机，8051是早期的最典型的代表作，由于MCS-51单片机影响极深远，许多公司都推出了兼容系列单片机，就是说MCS-51内核实际上已经成为一个8位单片机的标准。
其他的公司的51单片机产品都是和MCS-51内核兼容的产品而以。同样的一段程序，在各个单片机厂家的硬件上运行的结果都是一样的，如ATMEL的89C51（已经停产）、89S51， PHILIPS（菲利浦），和WINBOND（华邦）等，我们常说的已经停产的89C51指的是ATMEL公司的 AT89C51单片机，同时是在原基础上增强了许多特性，如时钟，更优秀的是由Flash（程序存储器的内容至少可以改写1000次）存储器取带了原来的ROM（一次性写入），AT89C51的性能相对于8051已经算是非常优越的了。
不过在市场化方面，89C51受到了PIC单片机阵营的挑战，89C51最致命的缺陷在于不支持ISP（在线更新程序）功能，必须加上ISP功能等新功能才能更好延续MCS-51的传奇。89S51就是在这样的背景下取代89C51的，现在，89S51目前已经成为了实际应用市场上新的宠儿，作为市场占有率第一的Atmel目前公司已经停产AT89C51，将用AT89S51代替。89S51在工艺上进行了改进，89S51采用0.35新工艺，成本降低,而且将功能提升,增加了竞争力。89SXX可以像下兼容89CXX等51系列芯片。同时，Atmel不再接受89CXX的定单，大家在市场上见到的89C51实际都是Atmel前期生产的巨量库存而以。
89S51相对于89C51增加的新功能包括：
-- 新增加很多功能，性能有了较大提升，价格却基本不变，甚至比89C51更低！
-- ISP在线编程功能，这个功能的优势在于改写单片机存储器内的程序不需要把芯片从工作环境中剥离。是一个强大易用的功能。
-- 工作频率为33MHz，大家都知道89C51的极限工作频率只有24M，就是说S51具有更高工作频率，从而具有了更快的计算速度。
-- 具有双工UART串行通道。
-- 内部集成看门狗计时器，不再需要像89C51那样外接看门狗计时器单元电路。
-- 双数据指示器。
-- 电源关闭标识。
-- 全新的加密算法，这使得对于89S51的解密变为不可能，程序的保密性大大加强，这样就可以有效的保护知识产权不被侵犯。
-- 兼容性方面：向下完全兼容51全部字系列产品。比如8051、89C51等等早期MCS-51兼容产品。也就是说所有教科书、网络教程上的程序（不论教科书上采用的单片机是8051还是89C51还是MCS-51等等），在89S51上一样可以照常运行，这就是所谓的向下兼容。
AT89S51看门狗程序例子如下：
AJMP MAIN
MAIN:
;启动看门狗
Mov 0A6H,#01EH ;先送1E
Mov 0A6H,#0E1H ;后送E1
;主程序************************************************************
;******************************************************************
START:
ACALL WDT ;调用复位看门狗子程序
AJMP START
;主程序************************************************************
;******************************************************************
;复位看门狗子程序
WDT:
Mov 0A6H,#01EH ;先送1E
Mov 0A6H,#0E1H ;后送E1
RET
END
注意事项：
1． 89S51的看门狗必须由程序激活后才开始工作。所以必须保证CPU有可靠的上电复位。
否则看门狗也无法工作。
2． 看门狗使用的是CPU的晶振。在晶振停振的时候看门狗也无效。
3． 89S51只有14位计数器。在16383个机器周期内必须至少喂狗一次。而且这个时间是固
定的，无法更改。当晶振为12M时每16个毫秒需喂狗一次。本回答被网友采纳
帮忙写下英文写作项目管理(建筑)120字左右
有项目管理系统相关的 英文文献 BCWS Budgeted Cost of Work Scheduled中文全称：计划工程预算成本 BCWP Budgeted Cost of work Performed 已执行工作预算成本 ACWP Allcom Cooperation Work Platform,全通数码管理 CV Curriculum Vitae履历 CSV COMMA SEPARATED VALUE，档案总管中的档案类型 CPI ConsumerPriceInd...
建筑施工安全管理的文献综述怎么写啊 跪求
首先,人员因素方面表现为:项目经历学历不高,粗放式管理,缺少系统培训;后勤人员分工不明确,找不到责任人;汪汪往指派与业主有一定社会关系的人员担任项日经理,但工程管理经验不足。 其次,材料因素方面表现为:没有按照设计、业主或监理的要求进货,不符合工程施工的要求;材料进场没有进行检验或匆忙检验,导致用不合格材料...
求关于建筑工程管理方面中英文对照文章一篇
2.1.1外部环境的影响外部环境的影响包括工程设计多变、工期的确定受行政干扰多、工程进度付款没有与网络计划紧密联系、工程款拖欠等。工程设计经常变化给网络计划的制定和调整带来了很大的困难,使施工企业应接不暇,无法使用网络计划实行施工管理;有些工程建设期限的确定违反科学规律,工程竣工日期一再提前也使企业无法按网...
工程造价参考文献中文40篇+英文10篇
[40]（具体信息略）二、英文文献 [1]Goldberg H E深入研究建筑信息模型（BIM）在建筑与工程界的潜在技术进化，发表于2004年《Cadalyst》，第21卷第11期，56-61页。[2]Nour M与Beucke K提出开放平台处理IFC模型版本的方法，发表于2008年《Tsinghua Science and Technology》，第13卷s1期，126-131页。
你好啊,求一片建筑方面的英文文献
一篇文献调查认为典型的二阶分析法忽视了许多重要的特性和实践设计需要，包括构件初始不完整性和它的方向，线性和非线性模型之间的一致性因为需要对每构件几个元件作二阶分析，和沿构件的负载。建议的方法包括这些条款以便它能直接用于实现高等分析要求的设计和应用钢框架。
求一篇土木工程英文文献翻译,毕业设计用的
外地办事处,围栏,桥梁和其他临时建筑,公共设备,如天然气,电力管道,水管,都连接到建筑上。最后,是建筑物内部的打扫和清洗。 业主的代表,会给建设工程作最后检查。如果他们满意并认为符合合同文件,那么业主接受该项目,并交给总承包商的一个占用证书,这表明,总承包商已完成建设,建设部门再根据建筑规范的要求发放最后...
100分求一篇建筑方面的期刊或报纸英文文献 5000字左右
日光建筑
建筑工程安全管理的参考文献有哪些?
5、姚勇. 浅谈新时期如何加强建筑工程安全监督管理[J]. 大陆桥视野, 2011(12):33-34.6、宗明珠付杰. 建筑工程安全管理[J]. 科学时代, 2011(7):145-146.7、刘柏茹. 导线测量的精度控制探讨[J]. 硅谷, 2009,(05) .8、 郭宗河,郑进凤,贺可强. 全站仪导线测量若干问题的探讨[J]. 合肥工业...
求建筑工程安全管理的参考文献
[8] 李亚奇康崇杰和. 论建筑工程全过程安全管理[J]. 时代经贸（学术版）, 2011(17):129.[9] 王晓鹍. 浅析建筑工程施工后期安全管理[J]. 甘肃科技, 2011,27(17):120-121.[10] 邓润华. 浅谈建筑工程安全管理[J]. 建材发展导向, 2011(7):66-67.[11] 梁立峰. 建筑工程安全生产管理...
关于“建筑工程项目工程变更管理”的翻译
In construction, due to the complexity, long-term and dynamic nature of the project implementation, project changes are inevitable. Project changes have great destructive to the contract price and contract term, and successful management is significant to the success of the project term ...
相似回答
