VHDL程序中逻辑左移和右移问题

Question

xilinix ISE 11.5下编写的程序，除了用下面的方法使数据左移和右移，怎样用SLL和SRL指令实现同样的效果？（注释部分的SLL和SRL指令编译不能通过）

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

PACKAGE GlobalDefinitions IS
CONSTANT cDataWidth : NATURAL :=8;
CONSTANT cAddrWidth : NATURAL :=5;
CONSTANT cOpCodewidth : NATURAL :=3;

SUBTYPE tDataBus IS STD_LOGIC_VECTOR(cDataWidth-1 DOWNTO 0);
SUBTYPE tAddr IS STD_LOGIC_VECTOR(cAddrWidth-1 DOWNTO 0);
SUBTYPE tOpCode IS STD_LOGIC_VECTOR(cOpCodewidth-1 DOWNTO 0);

CONSTANT cROL : tOpCode :="000";
CONSTANT cROR : tOpCode :="001";
CONSTANT cADD : tOpCode :="011";
CONSTANT cAND : tOpCode :="100";
CONSTANT cLDA : tOpCode :="101";
CONSTANT cSTA : tOpCode :="110";
CONSTANT cJMP : tOpCode :="111";
CONSTANT cSKZ : tOpCode :="010";

END GlobalDefinitions;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--USE IEEE.numeric_std.ALL
--USE IEEE.STD_LOGIC_ARITH.ALL;
USE WORK.GlobalDefinitions.ALL;

ENTITY ALU IS
PORT(accin : IN tDataBus;
opcode : IN tOpCode;
din : IN tDataBus;
zero : OUT STD_LOGIC;
dout : OUT tDataBus);
END ALU;

ARCHITECTURE behavior OF ALU IS
BEGIN
WITH opcode SELECT
dout <= accin(cDataWidth-2 DOWNTO 0)&accin(cDataWidth-1)WHEN cROL,
accin(0)&accin(cDataWidth-1 DOWNTO 1) WHEN cROR,
--accin SLL 1 WHEN cROL,
--accin SRL 1 WHEN cROR,
accin+din WHEN cADD,
accin AND din WHEN cAND,
accin WHEN cSTA,
din WHEN cLDA,
accin WHEN OTHERS;

zero <= '1' WHEN (accin = 0) ELSE
'0';
END behavior;

Answer 1

accin定义的输入类型出现错误，sll的操作数必须是BIN或布尔型一维数组。

Answer 2

在ieee的包集合中只定义了signed和unsigned类型的移位运算符 对于其他数据类型 目前还没有定义 若在综合器或者仿真器要对其他类型的数据使用移位运算符 可使用如下方法：
若A=“10010101”
A sll 2 描述为A<=A(5 DOWNTO 0)&"00";
A SLA描述为A<=A(5 DOWNTO 0)&A(0)&A(0);

追问

怎样才能用signed和unsigned类型实现移位运算？