关于VHDL实现移位寄存器问题，急等
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shift is
port
(data:in std_logic_vector(3 downto 0);
s:in std_logic_vector(1 downto 0);
clk,rst:in std_logic;
sr,sl:
q:out std_logic_vector(3 downto 0));
end shift;
architecture arc_shift of shift is
signal q1:std_logic_vector(3 downto 0);
begin
process(clk,rst)
begin
if(rst='1')then
q1<="0000";
elsif clk'event and clk='1'then
case s is
when"01"=>q1<=sr&q1(3 downto 1);
when"10"=>q1<=q1(2 downto 0)&sl;
when "11"=>q1<=data;
when others=>null;
end case;
end if;
end process;
q<=q1;
end arc_shift;
求大神给看看到底哪里的问题
Error (10500): VHDL syntax error at shudian.vhd(10) near text ":"; expecting ";", or ")"
Info: Found 0 design units, including 0 entities, in source file shudian.vhd
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 1 error, 0 warnings
Error: Peak virtual memory: 304 megabytes
Error: Processing ended: Sat May 09 14:39:16 2015
Error: Elapsed time: 00:00:00
Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings
quartusII上是这么说的，可是没有发现哪里有为题啊。。。。在线急等求解答
