vhdl报错

Question

entity v2114 is
Port ( d : inout STD_LOGIC_VECTOR (3 downto 0);
adr1 : in STD_LOGIC_VECTOR (4 downto 0);
adr2 : in STD_LOGIC_VECTOR (4 downto 0);
wr : in STD_LOGIC;
cs : in STD_LOGIC;
rd : in STD_LOGIC);
end v2114;

architecture Behavioral of v2114 is
type ram1 is array (32 to 0,32 downto 0) of STD_LOGIC ;
type ram2 is array (32 to 0,32 downto 0) of STD_LOGIC ;
type ram3 is array (32 to 0,32 downto 0) of STD_LOGIC;
type ram4 is array (32 to 0,32 downto 0) of std_logic ;
signal sram1 : ram1;
signal sram2 : ram2;
signal sram3 : ram3;
signal sram4 : ram4;
begin
process (cs,wr,rd,adr1,adr2,d)
begin
if(cs='0' and wr='0') then
sram1 (conv_integer (adr1), conv_integer (adr2))<=d(0);
sram2 (conv_integer (adr1) ,conv_integer (adr2))<=d(1);
sram3 (conv_integer (adr1),conv_integer (adr2))<=d(2);
sram4 (conv_integer (adr1),conv_integer (adr2))<=d(3);

end if;
end process;

d(0)<=sram1 (conv_integer (adr1),conv_integer (adr2)) when cs='0' and rd='0' else 'Z';
d(1)<=sram2 (conv_integer (adr1),conv_integer (adr2)) when cs='0' and rd='0' else 'Z';
d(2)<=sram3 (conv_integer (adr1),conv_integer (adr2)) when cs='0' and rd='0' else 'Z';
d(3)<=sram4 (conv_integer (adr1),conv_integer (adr2)) when cs='0' and rd='0' else 'Z';
end Behavioral;
实现的是2114的外部结构
Static elaboration of top level VHDL design unit v2114 in library work failed 。以及在这一句
sram1 (conv_integer (adr1), conv_integer (adr2))<=d(0);出现 No index value can belong to null index range

Answer 1

我试着用Quartus II编译了一下，没有错啊
前面我自己加了
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
只是有28个警告

追问

No index value can belong to null index range在if(cs='0' and wr='0') then下一行报的错