急求大神用VHDL编写程序，非常感谢!!!具体如下面的图片……

Answer 1

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;

ENTITY adder_8 IS
GENERIC (n: Positive :=8);
PORT(a,b: IN std_logic_vector(n-1 DOWNTO 0);
c_in: IN std_logic;
sum: OUT std_logic_vector(n-1 DOWNTO 0);
c_out: OUT std_logic);
END adder_8;
ARCHITECTURE adder OF adder_8 IS
SIGNAL carry: std_logic_vector(n-1 DOWNTO 1);
BEGIN
PROCESS(a,b,c_in)
VARIABLE carry,ta,tb,sum_t: std_logic_vector(n DOWNTO 0);
BEGIN
carry := (OTHERS => '0');
carry(0) := c_in;
ta := '0'&a;
tb := '0'&b;
sum_t := ta+tb+carry;
sum <= sum_t(n-1 DOWNTO 0);
c_out <= sum_t(n);
END PROCESS;
END adder;