vhdl程序总有错误，怎么解决

Question

错误如下：Error (10483): VHDL error at ajcl.vhd(16): can't infer register for signal "keyout[7]" because signal does not hold its value outside clock edge
源代码
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ajcl IS
PORT (clk,clr:IN STD_LOGIC;
key_o,key_1,key_2,key_3,key_4,key_5,key_6,key_7,key_8,key_9:IN STD_LOGIC;
add,sub,equ:IN STD_LOGIC;keyout:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
opout,press_num,press_op,press_equ:OUT STD_LOGIC);
END ajcl;
ARCHITECTURE rtl OF ajcl IS
BEGIN
PROCESS(clk)
VARIABLE key:STD_LOGIC_VECTOR(9 DOWNTO 0) ;
BEGIN
IF(clr='1')then keyout<= "00000000";press_num<='0';opout<='0';
press_op<='0';press_equ<='0';
elsif (clk' event and clk='1')then
key:= key_o&key_1&key_2&key_3&key_4&key_5&key_6&key_7&key_8&key_9;
elsif key = "1000000000" then keyout<= "00000000"; press_num<='1';
elsif key= "0100000000" then keyout<= "00000001"; press_num<='1';
elsif key= "0010000000" then keyout<= "00000010"; press_num<='1';
elsif key= "0001000000" then keyout<= "00000011"; press_num<='1';
elsif key= "0000100000" then keyout<= "00000100"; press_num<='1';
elsif key= "0000010000" then keyout<= "00000101"; press_num<='1';
elsif key= "0000001000" then keyout<= "00000110"; press_num<='1';
elsif key= "0000000100" then keyout<= "00000111"; press_num<='1';
elsif key= "0000000010" then keyout<= "00001000"; press_num<='1';
elsif key= "0000000001" then keyout<= "00001001" ; press_num<='1';
else keyout<= "00000000"; press_num<='0';

Answer 1

这个写法是错误的。VHDL程序在进程里面是顺序执行的，你的原始程序可以分成
if reset='1' then
c_st<=s0;
end if;
和
if clk='1'and clk'event then
这两个部分，if reset='1' then 这一部分其实没有起作用。
c_st又需要在电平触发，有需要沿触发，这个是没办法综合，这个就是你错误的原因。
你的本意是状态机在复位的时候初态是S0，然后不复位的时状态转换，所以稍微改一下就行了。