vhdl中元件例化语句端口映射可以直接映射为‘0’吗？

Question

u1: shift_register_ip port map
(
aclr => '0',
clken=> clken,
clock =>clock,
shiftin =>shiftin_1,
shiftout=>shiftout_1,
taps0x =>mid0x,
taps1x =>mid1x,
taps2x =>mid2x,
taps3x =>mid3x,
taps4x =>mid4x,
taps5x =>mid5x,
taps6x =>mid6x,
taps7x =>mid7x
);

Answer 1

可以直接映射为‘0‘。但通常是在结构体中声明一个信号，并将该信号赋值为‘0’，同时映射aclr到该信号。