Error (10500): VHDL syntax error at display.vhd(25) near text "process"; expecting "if" 急求解啊

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity display is
port( cp1:in std_logic;
overflow: in std_logic;
low1: in std_logic;
p0, p1 ,p2,p3:in integer range 0 to 9;
show:out std_logic_vector(6 downto 0);
sel:out std_logic_vector(3 downto 0));
end display;

architecture behavior of display is
signal count: integer range 0 to 3;
signal sel_1:std_logic_vector(3 downto 0);
begin
process(cp1)
begin
if cp and cp='1' then
if count=3 then count<=0;
else count<= count+1;
end else;
end if;
end process;
process(count)
begin
case count is
when 0=>sel_1<="1110";
when 1=>sel_1<="1101";
when 2=>sel_1<="1011";
when 3=>sel_1<="0111";
end case;
end if;
process(low1,overflow)
begin
if (low='1') then
show<="1111110";
elsif (overflow ='1') then
show<="1000111";
elsif (sel_1(0)='0') then
case p0 is
when 0=>show<="1111110";
when 1=>show<="0110000";
when 2=>show<="1101101";
when 3=>show<="1111001";
when 4=>show<="0110011";
when 5=>show<="1011011";
when 6=>show<="0011111";
when 7=>show<="1110000";
when 8=>show<="1111111";
when 9=>show<="1110011";
end case;
elsif (sel_1(1)='0') then
case p1 is
when 0=>show<="1111110";
when 1=>show<="0110000";
when 2=>show<="1101101";
when 3=>show<="1111001";
when 4=>show<="0110011";
when 5=>show<="1011011";
when 6=>show<="0011111";
when 7=>show<="1110000";
when 8=>show<="1111111";
when 9=>show<="1110011";
end case;
elsif (sel_1(2)='0') then
case p2 is
when 0=>show<="1111110";
when 1=>show<="0110000";
when 2=>show<="1101101";
when 3=>show<="1111001";
when 4=>show<="0110011";
when 5=>show<="1011011";
when 6=>show<="0011111";
when 7=>show<="1110000";
when 8=>show<="1111111";
when 9=>show<="1110011";
end case;
elsif (sel_1(3)='0') then
case p3 is
when 0=>show<="1111110";
when 1=>show<="0110000";
when 2=>show<="1101101";
when 3=>show<="1111001";
when 4=>show<="0110011";
when 5=>show<="1011011";
when 6=>show<="0011111";
when 7=>show<="1110000";
when 8=>show<="1111111";
when 9=>show<="1110011";
end case;
end if;
end process;
sel<=sel_1;
end;

首先cp没有定义,只看到以个cp1,在第一个if中and的前面是错的,如果你是想判断上升沿的话应该是cp1'event and cp1='1'然后不应该是end else,是end if,在34行前面都没有if突然就出来一个end if,应该是end process,37行突然来了个没定义的low,应该是low1吧~~其他好像就没什么错误了
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第1个回答  2013-05-24
VHDL就没有过“end else;”这样的语句,你把这句删掉!追问

24 near text "process"; expecting "if"
26 "begin"; expecting ":=", or "<="
34"process"; expecting "end", or "(", or an identifier
35"begin"; expecting ":=", or "<="
怎么还有这么多错误啊 麻烦你帮我看看

追答

"if cp and cp='1' then"是什么意思?

应当是IF (cp'Event AND cp='1') THEN才对吧。

...error at display.vhd(25) near text "process"; expecting "if" 急...
首先cp没有定义,只看到以个cp1,在第一个if中and的前面是错的,如果你是想判断上升沿的话应该是cp1'event and cp1='1'然后不应该是end else,是end if,在34行前面都没有if突然就出来一个end if,应该是end process,37行突然来了个没定义的low,应该是low1吧~~其他好像就没什么错误了 ...

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