library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity display is
port( cp1:in std_logic;
overflow: in std_logic;
low1: in std_logic;
p0, p1 ,p2,p3:in integer range 0 to 9;
show:out std_logic_vector(6 downto 0);
sel:out std_logic_vector(3 downto 0));
end display;
architecture behavior of display is
signal count: integer range 0 to 3;
signal sel_1:std_logic_vector(3 downto 0);
begin
process(cp1)
begin
if cp and cp='1' then
if count=3 then count<=0;
else count<= count+1;
end else;
end if;
end process;
process(count)
begin
case count is
when 0=>sel_1<="1110";
when 1=>sel_1<="1101";
when 2=>sel_1<="1011";
when 3=>sel_1<="0111";
end case;
end if;
process(low1,overflow)
begin
if (low='1') then
show<="1111110";
elsif (overflow ='1') then
show<="1000111";
elsif (sel_1(0)='0') then
case p0 is
when 0=>show<="1111110";
when 1=>show<="0110000";
when 2=>show<="1101101";
when 3=>show<="1111001";
when 4=>show<="0110011";
when 5=>show<="1011011";
when 6=>show<="0011111";
when 7=>show<="1110000";
when 8=>show<="1111111";
when 9=>show<="1110011";
end case;
elsif (sel_1(1)='0') then
case p1 is
when 0=>show<="1111110";
when 1=>show<="0110000";
when 2=>show<="1101101";
when 3=>show<="1111001";
when 4=>show<="0110011";
when 5=>show<="1011011";
when 6=>show<="0011111";
when 7=>show<="1110000";
when 8=>show<="1111111";
when 9=>show<="1110011";
end case;
elsif (sel_1(2)='0') then
case p2 is
when 0=>show<="1111110";
when 1=>show<="0110000";
when 2=>show<="1101101";
when 3=>show<="1111001";
when 4=>show<="0110011";
when 5=>show<="1011011";
when 6=>show<="0011111";
when 7=>show<="1110000";
when 8=>show<="1111111";
when 9=>show<="1110011";
end case;
elsif (sel_1(3)='0') then
case p3 is
when 0=>show<="1111110";
when 1=>show<="0110000";
when 2=>show<="1101101";
when 3=>show<="1111001";
when 4=>show<="0110011";
when 5=>show<="1011011";
when 6=>show<="0011111";
when 7=>show<="1110000";
when 8=>show<="1111111";
when 9=>show<="1110011";
end case;
end if;
end process;
sel<=sel_1;
end;
24 near text "process"; expecting "if"
26 "begin"; expecting ":=", or "<="
34"process"; expecting "end", or "(", or an identifier
35"begin"; expecting ":=", or "<="
怎么还有这么多错误啊 麻烦你帮我看看
"if cp and cp='1' then"是什么意思?
应当是IF (cp'Event AND cp='1') THEN才对吧。
...error at display.vhd(25) near text "process"; expecting "if" 急...
首先cp没有定义,只看到以个cp1,在第一个if中and的前面是错的,如果你是想判断上升沿的话应该是cp1'event and cp1='1'然后不应该是end else,是end if,在34行前面都没有if突然就出来一个end if,应该是end process,37行突然来了个没定义的low,应该是low1吧~~其他好像就没什么错误了 ...
...出现错误啊Error (10500): VHDL syntax error at shizhong.vhd(20...
元件例化不能用在进程里面,只能用在结构体中!!!
Error (10500): VHDL syntax error at
你的描述是Verilog HDL,但文件名后缀却是.vhd,所以出现编译错误。关闭文件后,将后缀改成.v就行。
Error (10500): VHDL syntax error at count.vhd(33) near text "PROCE...
错误(10500):硬件描述语言(VHDL)语法错误在计数vhd(33)接近文本“进程”,希望“如果”
Error (10500): VHDL syntax error at digital.vhd(174) near text...
第四句 elsif(a='1') then 改成 if(a='1') then,不然最后的end if;就成了多余的了。
Error (10500): VHDL syntax error at JSQ.vhd(24) near text ?_百度...
你的单引号和双引号全用了中文标点符号了,把它们改成英文标点就行了。
VHDL编译错误
Error (10500): VHDL syntax error at p2r_CordicPipe.vhd.vhd(58) near text "compatibility"; expecting "begin", or a declaration statement “compatibility with Xilinx WebPack ”这一行,你用的Xilinx器件,是不是应该用 ModleSim (参考http:\/\/www.edacn.net\/bbs\/thread-68737-1-1.html...
VHDLError (10500): VHDL syntax error at max.vhd(20) near text...
在VHDL中,信号(SIGNAL)表示硬件中的“连线”,而端口(PORT)是设计实体对外的连线。只有在声明端口时,才需要声明信息的流向,而声明实体内部的连线时,不要声明信息流向,因为这根连线上的信息应当既不流出实体也不流入实体。所以声明信号tmp1和tmp2时,只需声明信号的类型,而不要声明信息的流向,...
VHDLError (10500): VHDL syntax error at max.vhd(20) near text...
在VHDL中,信号(SIGNAL)表示硬件中的“连线”,而端口(PORT)是设计实体对外的连线。只有在声明端口时,才需要声明信息的流向,而声明实体内部的连线时,不要声明信息流向,因为这根连线上的信息应当既不流出实体也不流入实体。所以声明信号tmp1和tmp2时,只需声明信号的类型,而不要声明信息的流向,...
Error (10500): VHDL syntax error at DFF2.vhd(7) near text "END...
zuoye1.vhd 这个是你的文件名 应该与工程名一样的 你要重新新建工程,工程名decoder_3_to_8 保存为decoder_3_to_8.vhd