使用VHDL的CASE语句，设计七段译码器程序，

Question

求解电路语言。使用VHDL的CASE语句，设计七段译码器程序，实现显示0-9的数字。请高手注释一下，方便本人能看懂，因为本人要去实践应用的。谢谢。

Answer 1

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CL IS
PORT ( Q : IN STD_LOGIC_VECTOR(3 DOWNTO 0); ----输入4位BCD码 DOUT : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); --7段码
END CL; ARCHITECTURE behav OF CL IS
BEGIN
PROCESS(Q) BEGIN
CASE Q IS
WHEN "0000"=> DOUT<="0111111";
WHEN "0001"=> DOUT<="0000110";
WHEN "0010"=> DOUT<="1011011";
WHEN "0011"=> DOUT<="1001111";
WHEN "0100"=> DOUT<="1100110";
WHEN "0101"=> DOUT<="1101101";
WHEN "0110"=> DOUT<="1111101";
WHEN "0111"=> DOUT<="0000111";
WHEN "1000"=> DOUT<="1111111";
WHEN "1001"=> DOUT<="1101111";
WHEN "1111"=> DOUT<="0000000";
WHEN "1101"=> DOUT<="1000000";
WHEN OTHERS=> DOUT<="0000001";
END CASE;
END PROCESS;
END behav;