2-4译码器的VHDL描述

Question

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY decoder24 IS
PORT(s1,s2:IN bit;
m:OUT bit_vector(3 downto 0));
END;
ARCHITECTURE be OF decoder24 IS
BEGIN
process(s1,s2)
BEGIN
if s1='0' and s2='0'
then m :<= '0001';
elseif s1='0' and s2='1'
then m :<= '0010';
elseif s1='1' and s2='0'
then m :<= '0100';
elseif s1='1' and s2='1'
then m :<= '1000';
END if;
END process;
END;

Answer 1

1.端口是bit类型，无需声明IEEE库和IEEE.STD_LOGIC.1164程序包。
2.2-4译码器不是优先级结构，应当用case语句描述。
3.字符串文字应当使用双引号。
4.信号赋值号是“<=”，而不是“:<=”。
ENTITY decoder24 IS
PORT(s1,s2:IN bit;
m:OUT bit_vector(3 downto 0));
END;
ARCHITECTURE be OF decoder24 IS
BEGIN
process(s1,s2)
BEGIN
case s1&s2 is
when "00" => m <= "0001";
when "01" => m <= "0010";
when "10" => m <= "0100";
when "11" => m <= "1000";
when others => m <= (others => '0');
end case;
END process;
END;