xilinx ISE verilog testfixture 不出波形 我用的是13.1的版本，激励源应该没错，我把程序贴出来，求解答

Question

module test_counter(rst_n,clk,signal
);
input rst_n,clk;
output signal;

reg signal;
reg [5:0] count;

always@(posedge clk)
if(!rst_n)
begin
count <= 0;
signal <= 0;

end
else
begin
if( count == 19)
begin
count <= 0;
signal <= ~signal;
end
else
count <= count+1;
end

endmodule

下面是激励 textfisture
initial begin
// Initialize Inputs
rst_n = 0;
clk = 0;

// Wait 100 ns for global reset to finish
#100;
rst_n = 1;
clk =0;
// Add stimulus here
forever #100 clk = ~clk;
#10000 $finish;
end

Answer 1

textfisture加入这个：

test_counter inst(
.rst_n(rst_n),
.clk(clk),
.signal(signal)
);

而且你仿真顶层模块一定是textfisture模块，不要是test_counter模块。

Answer 2

可能是时钟的问题，可以将时钟写到initial模块外面。
always
begin
#100 clk = 0;
#100 clk = 1;
end

Answer 3

把rst_n和clk分开来写，
initial begin
rst_n = 0;
#100;
rst_n = 1;
#10000
$finish;
end

initial begin
clk = 0;
forever #100 clk = ~clk;
end