VHDL LOOP循环问题

Question

各位高手，下面是我编的程序的一部分，我在进程中用了三个loop，为什么会报这样一个错误Error (10536): VHDL Loop Statement error at G.vhd(45): loop must terminate within 10,000 iterations

下面是我程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity G is
port(clk : in std_logic;
data_out : out std_logic);
end G;

architecture one of G is
signal count:integer range 0 to 90 :=0;
signal cnt:integer range 0 to 1500 :=0;
signal data_r:std_logic_vector(7 downto 0);
signal data_g:std_logic_vector(7 downto 0);
signal data_b:std_logic_vector(7 downto 0);
signal num_r:integer range 0 to 8 :=0;
signal num_g:integer range 0 to 8 :=0;
signal num_b:integer range 0 to 8 :=0;

begin
p1:process(clk)
begin
if clk'event and clk='1' then
if count<90 then
count<=count+1;
else
count<=0;
end if;

if cnt<1500 then
cnt<=cnt+1;
else
cnt<=0;
end if;
end if;
end process p1;

p2:process(count,cnt,data_r,data_g,data_b,num_r,num_g,num_b)
begin
data_r<="11111111";
data_g<="00000000";
data_b<="00000000";

L1:loop
if data_r(num_r)='1' then
case count is
when 0 to 60 => data_out<='1';
when 61 to 90 => data_out<='0';
end case;
else
case count is
when 0 to 30 => data_out<='1';
when 31 to 90 => data_out<='0';
end case;
end if;
num_r<=num_r+1;
exit L1 when num_r=8;
end loop;

L2:loop
if data_g(num_g)='1' then
case count is
when 0 to 60 => data_out<='1';
when 61 to 90 => data_out<='0';
end case;
else
case count is
when 0 to 30 => data_out<='1';
when 31 to 90 => data_out<='0';
end case;
end if;
num_g<=num_g+1;
exit L2 when num_g=8;
end loop;

L3:loop
if data_b(num_b)='1' then
case count is
when 0 to 60 => data_out<='1';
when 61 to 90 => data_out<='0';
end case;
else
case count is
when 0 to 30 => data_out<='1';
when 31 to 90 => data_out<='0';
end case;
end if;
num_b<=num_b+1;
exit L3 when num_b=8;
end loop;

if num_b=8 then
case cnt is
when 0 to 1500 => data_out<='0';
end case;
end if;

end process p2;
end one;

Answer 1

因为loop中计数值的数据类型必须是“变量”。应该把num_r,num_g,num_b的数据类型改为变量。虽然可能楼主看不到。

Answer 2

建议你在把VHDL的语法看看再自己改吧，不仅仅是一个LOOP 的问题，还有其他的的语句都是VHDL不支持的

例如：
case count is
when 0 to 60 => data_out<='1';
when 61 to 90 => data_out<='0';
end case;

这个 WHEN 0 TO 60

追问

WHEN 0 to 60为何不行？，我是延时用的，除去loop那些编译完全通过的。我的板子频率50MHZ，也就是1clk为0.02纳秒，when 0 to 60刚好是记了61个数，也就是0.02*61纳秒，这是给另外一个芯片的时序输入，下板验证完全可以，芯片接收时序完全正确，可以正常工作

追答

你说能用那就用吧，我孤陋寡闻了

Answer 3

你这问题大的去了....乱七八糟，从哪你复制来的啊？
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
。。。
。。。
后面也是一片错,输入输出端口一个都没定义,完全乱的.....

追问

这个程序是我自己写，请不要怀疑我是抄的，只是我一直用惯了C，现在编VHDL难免有点C的倾向，为什么说我输入输出端口一个都没定义？那我在实体里不是定义了输入是个时钟信号，输出也是std_logic了吗?