VHDL中loop语句的问题,急求！！！！！！！！！！！！！！！！！1

Question

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity jifenqi is
port (clk:in std_logic;
rst,d1,d2,d3,d4:in std_logic;--按键

enled,shuma,en:out std_logic_vector(7 downto 0);
beer:out std_logic--蜂鸣器 );
end entity;
architecture beh of jifenqi is
type data is array (0 to 9) of std_logic_vector(7 downto 0);
signal count :integer range 0 to 99;
constant mystore:data:=("11000000","11111001","10100100","10110000","10011001","10010010","10000010","11111000","10000000","10010000");
signal qq:integer range 0 to 49999999;
signal jie:integer range 1 to 4;
signal miao,fen:integer range 0 to 60;
signal djs:integer range 0 to 24;
begin
process(clk,rst)
begin
if(rst='0')then jie<=1;
djs<=24;
enled<="11111111";
en<="00000000";
shuma<=mystore(0);
shuma<=mystore(0);
elsif(clk'event and clk='1') then
en<="11111111";
qq<=qq+1;
if(qq=49999999)then
qq<=0;
miao<=miao+1;
if(miao=60)then
miao<=0;
fen<=fen+1;
djs<=djs-1;
if(djs=0)then
djs<=24;
end if;
if(fen=12) then
fen<=0;
beer<='0';
if(miao=10) then
beer<='1';
end if; jie<=jie+1;
if(jie=5)then
enled<="11111111";
end if;
end if;
end if;
end if;
end if;
if( d1='0')then
count<=count+1;
w:loop
count<=count;
exit w when count>10;
end loop w; 这是我写的VHDL程序，综合时总是报错 loop must
terminate at or before 10000 iterations

Answer 1

你这个程序怎么看都像是C写法，硬件描述语言完全不是这么用的。。。如果是希望count增加到10就产生一个信号的话可以直接写成

if( d1='0')then
if(count=10)then
count<=(others=>'0');
temp<='1';
else
count<=count+1;
temp<='0';
end if;
end if;