vhdl编程问题

Question

--JJS.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY JJS IS
PORT(CLKS,START,RES,TEST:IN STD_LOGIC;
IN1,IN2,IN3,IN4:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
LIGHT:OUT STD_LOGIC;
OUT1,OUT2,OUT3,OUT4:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END;
ARCHITECTURE ONE OF JJS IS
SIGNAL Q1,Q2,Q3,Q4:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
PROCESS(START,CLKS,RES,TEST,Q4)
VARIABLE A:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
IF RES='0' OR TEST='0' THEN
Q1<="0000";Q2<="0000";Q3<="0000";Q4<="0000";
ELSIF Q4=(IN4-15) OR START='0' THEN A:="00";LIGHT<='0';
ELSIF START='1' THEN A:="11";LIGHT<='1';
CASE A IS
WHEN "11"=>IF CLKS'EVENT AND CLKS='1' THEN
IF(IN1-Q1)=0 THEN Q1<=(IN1-9);Q2<=Q2+1;
ELSE Q1<=Q1+1;
END IF;
IF(IN2-Q2)=0 AND (IN1-Q2)=0 THEN
Q3<=Q3+1;Q2<=(IN2-5);Q1<=(IN1-9);
END IF;
IF(IN3-Q3)=0 AND (IN2-Q2)=0 AND (IN1-Q1)=0 THEN
Q4<=Q4+1;Q3<=(IN3-9);Q2<=(IN2-5);Q1<=(IN1-9);
END IF;
IF(IN4-Q4)=0 AND (IN3-Q3)=0 AND (IN2-Q2)=0 AND (IN1-Q1)=0
THEN Q4<=(IN4-15);Q3<=(IN3-14);Q2<=(IN2-13);Q1<=(IN1-12);
END IF;
END IF;
WHEN OTHERS=>NULL;
END CASE;
END IF;
END PROCESS;
OUT1<=(IN1-Q1);
OUT2<=(IN2-Q2);
OUT3<=(IN3-Q3);
OUT4<=(IN4-Q4);
END;
提示第17行有错误
Error (10324): VHDL Expression error at JJS.vhd(18): expression ""0000"" has 4 elements ; expected 2 elements.

Answer 1

将SIGNAL Q1,Q2,Q3,Q4:STD_LOGIC_VECTOR(1 DOWNTO 0);改成SIGNAL Q1,Q2,Q3,Q4:STD_LOGIC_VECTOR(3 DOWNTO 0);吧，否则放不下4位逻辑向量。