请用VHDL设计一个分频器，从50Mhz信号分频出440HZ信号

Question

要有详细的程序（芯片：EP1C3T144C8)
完成后再重谢！！！

Answer 1

50000000/440 = 113636分频倍数
程序 如下
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity fp is
port(clk: in std_logic;
fpclk: out std_logic);
end fp;

architecture arc of fp is
begin
process(clk)
variable count: integer range 0 to 113636;
variable clk0: std_logic;
begin
if clk'event and clk='1' then
if count=113636 then
clk0:=not clk0;
count:=0;
else
count:=count+1;
end if;
end if;
fpclk<=clk0;
end process;
end arc;

Answer 2

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all;

entity clk_diver is
port ( rst,clk_in : in std_logic ; ---50M Hz
clk16x: out std_logic ---
) ;
end clk_diver ;

architecture v1 of clk_diver is

begin
---------------------
process (rst,clk_in)
variable n: std_logic_vector(17 downto 0):=(others =>'0');
begin
if rst = '1' then
clk16x <= '0' ;
n:=(others =>'0');
elsif clk_in 'event and clk_in = '1' then
----50,000,000/(16*115200) =113636.36
if n<=56818 then ---113636/2=56818
clk16x<='0';
n:=n+1;
elsif n<113636 then
clk16x<='1';
n:=n+1;
else
n:=(others =>'0');

end if;
end if ;
end process ;
----------------------------
end ;
直接计数分频，不就OK了？