VHDL语言中编译出现：Error (10500): VHDL syntax error at FPGA.vhd(7) near text "?;....具体见下：

Question

编译时出现以上或类似错误，请教下，，怎么改？？
源程序如下：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity clk_cnt is
port(
bclk:in std_logic; --标准频率时钟信号
xclk:in std_logic; --待测频率信号
gate:in std_logic; --预置门控制信号
clr:in std_logic; --清零和初始化信号
sel:in std_logic_vector(2 downto 0); --data select
databus：out std_logic_vector(7 downto 0) --计数器值输出
);
end clk_cnt;
architecture counter of clk_cnt is
signal bz_count, dc_count: std_logic_vector(31 downto 0); --基准计数器和待测频率计数器
signal bz_ena, dc_ena: std_logic; --允许计数使能
begin
process (sel) --读计数值进程
begin
case sel(2 downto 0) is
when "000"=>databus<=bz_count(7 downto 0); --标准频率信号计数值
when "001"=>databus<=bz_count(15 downto 8);
when "010"=>databus<=bz_count(23 downto 16);
when "011"=>databus<=bz_count(31 downto 24);
when "100"=>databus<=dc_count(7 downto 0); --待测频率信号计数值
when "101"=>databus<=dc_count(15 downto 8);
when "110"=>databus<=dc_count(23 downto 16);
when "111"=>databus<=dc_count(31 downto 24);
when others=>null;
end case;
end process;
bzcounter:process(bclk,clr,gate) --标准频率计数器进程
begin
if clr=′1′then bz_count<=(others=>′0′);
elsif rising_edge(bclk)then
if bz_ena=′1′then bz_count<=bz_count+1;
end if;
end if;
end process;
dccounter:process(xclk,clr,gate) --待测频率计数器进程
begin
if clr=′1′then dc_count<=(others=>′0′);
elsif rising_edge(xclk) then
if dc_ena=′1′then dc_count<=dc_count+1;
end if;
end if;
end process;
DQ: process(xclk,clr) --控制进程,D触发器
begin
if clr=′1′then dc_ena<=′0′;
elsif rising_edge(xclk) then
dc_ena<=gate;
end if;
end process;
bz_ena<=dc_ena;
end arch itecture;

错误显示：
Error (10500): VHDL syntax error at FPGA.vhd(7) near text ?
Error (10500): VHDL syntax error at FPGA.vhd(7) near text "?; expecting an identifier, or "constant", or "file", or "signal", or "variable"
很急，，在线等。。。。
其他错误提示与上述错误基本相同。。

Answer 1

端口声明语法错误，
bclk : in std_logic; -- :左右要有空格

Answer 2

端口声明语法错误