Such being the case, the bare silicon wafer CMP has progressed toward planarization polishing or CMP for LSI devices. However, the process applicable is supposed to vary depending on the LSI types. As is the case with the planarization by etch-back method, CMP is basically applied to the device, isolation, and interconnection processes on SiO2 film (oxide film) as interlevel dielectric layers, metal film (W, Al, Cu, etc.) as interconnection materials, and polycrystalline silicon (poly-Si) and single crystal silicon as capacitor materials.
Figure 7.9 shows a sectional diagram of a device and the processes to which planarization CMP is applied. From the bottom, they are STI CMP, interlevel dielectric (ILD) layer CMP, W-plug damascene CMP, and wiring metals (Al, Cu) damascene CMP. When the plug and ILD are formed simultaneously, it is termed a dual damascene CMP.
Figure 7.10 indicates Cu wiring process by the dual damascene method. Basic requirements for the wafer planarization in the device fabrication process and its related processing factors and conditions are shown in Table 7.5.