QuartusII Verilog HDL语法错误？

Question

下面的个程序为什么给寄存器赋值的时候，出现了语法错误。
module LED_Chinese(clk_H,ex_s,ex_l);
input clk_H;
output[15:0] ex_l;
reg[15:0] ex_l;
output[3:0] ex_s;
reg[3:0] ex_s;
reg[15:0] data[0:32];
data[0]='b0000000000000000;
data[1]='b0000000000010000;
data[2]='b0000000000010000;
data[3]='b0000000000010000;
data[4]='b0111111111111111;
data[5]='b1000000000010000;
data[6]='b0100000000010000;
data[7]='b0000011000010000;
data[8]='b0000000100010000;
data[9]='b0000000000010000;
data[10]='b0000000000010000;
data[11]='b0000000000000111;
data[12]='b1111111111111000;
data[13]='b0000000001100000;
data[14]='b0000000010000000;
data[15]='b0000000100000000;
always@(posedge clk_H)
begin
ex_s=ex_s+1;
ex_l=data[ex_s];
end
endmodule
错误如下：
Error (10170): Verilog HDL syntax error at LED_Chinese.v(8) near text "="; expecting ".", or an identifier, or "["
Error (10170): Verilog HDL syntax error at LED_Chinese.v(9) near text "="; expecting ".", or an identifier, or "["
Error (10170): Verilog HDL syntax error at LED_Chinese.v(10) near text "="; expecting ".", or an identifier, or "["
Error (10170): Verilog HDL syntax error at LED_Chinese.v(11) near text "="; expecting ".", or an identifier, or "["
Error (10170): Verilog HDL syntax error at LED_Chinese.v(12) near text "="; expecting ".", or an identifier, or "["

Answer 1

module LED_Chinese(clk_H,ex_s,ex_l,reset);
input clk_H;
input reset;
output[15:0] ex_l;
reg[15:0] ex_l;
output[3:0] ex_s;
reg[3:0] ex_s;
reg[15:0] data[0:32];

always@(posedge clk_H)
begin
if(reset) begin
data[0]<='b0000000000000000;
data[1]<='b0000000000010000;
data[2]<='b0000000000010000;
data[3]<='b0000000000010000;
data[4]<='b0111111111111111;
data[5]<='b1000000000010000;
data[6]<='b0100000000010000;
data[7]<='b0000011000010000;
data[8]<='b0000000100010000;
data[9]<='b0000000000010000;
data[10]<='b0000000000010000;
data[11]<='b0000000000000111;
data[12]<='b1111111111111000;
data[13]<='b0000000001100000;
data[14]<='b0000000010000000;
data[15]<='b0000000100000000;
ex_s<=1'b0;
ex_l<=32'b0;
end
else begin
ex_s<=ex_s+1;
ex_l<=data[ex_s];
end
end
endmodule

我修改了下，你可以试试看，应该是没有语法错误了，楼上说的挺对的
还有就是不可以采用阻塞赋值，应该采用非阻塞赋值的~~我已改过来了

Answer 2

1. data是reg型,不能在always外赋值.
2. ex_i, ex_s这些reg输出都需要在always里做初始化.

Answer 3

data[0]='b0000000000000000;这一句应该改成：data[0]=16'b0000000000000000;你是16位的数据嘛，前面需要注明的。

Answer 4

data这行你是要用数组来表示的吧，但这这样子你还不如单独拿出来例化一个模块呢。这样子是找不到了，其实你是把地址计数器和ROM给结合起来了吧。