quartus II Verilog hdl 编译出错

Question

报错啊Error (10170): Verilog HDL syntax error at fenpin.v(1) near text ";"; expecting ".", or an identifier

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpin is
port (clk : in std_logic；
reset：in std_logic;
newclk:out std_logic);
end fenpin;
architecture art of fenpin is
constant divided : integer:=6;
begin
divided_clk:process(clk) is
variable count :integer range 0 to 5;
begin
if(reset='1')then
count:=0
newclk<='0';
if clk'event and clk ='1'then
if(count<(divided/2))then
newclk<='1';
count:=count+1;
elsif(count<(divided-1))then
newclk<='0';
count:=count+1;
else
ccount:=0;

Answer 1

你的描述明明是VHDL嘛，怎么说是Verilog HDL呢？你把源文件名fenpin.v改成fenpin.vhd，然后重新编译试一试。